1. Field of the Invention
The present invention relates to a video signal processor which performs video conversion on digitalized video signals.
2. Description of the Related Art
There are video format conversions which enables to display a video being shot in a film such as a movie or a video signal formed by a CCD device which picks the image by the equivalent frame number (24 frames/second) on a TV set of NTSC type, or which enables the image or the video signal to be recorded on a recording device such as a VCR (Video Cassette Recorder). As an example of such video format conversions, known is a 2:3 pull-down system or 2:3:3:2 pull-down system. As for the pull-down format conversion, as disclosed in Japanese Unexamined Patent Publication No. 2003-284007, known is the one in which the format conversion on an input side and an output side by a respective synchronous system, so as to smoothen the visibility of the video after the format conversion.
By performing such video format conversion, a progressive video signal (referred to as 24P video signal hereinafter) formed by 24 frames/second can be finely converted to an interlace signal (referred to as 60I video signal) formed by 60 fields/second) for the TV set of NTSC type and the VCR device. Thereby, while being the 60I video signal, a visual effect as of the movie film (24P video signal) can be obtained.
An example of the video conversion by the 2:3:3:2 pull-down system will be described by referring to FIG. 12 and FIG. 13.
FIG. 12 is a video block diagram showing the configuration of a video signal processor which converts the 24P video signal to the 60I video signal. In FIG. 12, reference numeral 71 is an input terminal of the 24P video signal, 72 is an input terminal of a frame synchronizing signal of the 60I video signal, 74, 75 are frame memories, 76 is a frame memory writing/reading-out controller, 77 is a memory output selector, 78 is a pull-down controller and 79 is an output terminal of the 60I video signal.
FIG. 13 is a timing chart of the case where the conversion of the 2:3:3:2 pull-down system is performed using the configuration of FIG. 12. In FIG. 13, reference numeral 81 shows the timing of the frame synchronizing signal of the 24P video signal, 82 shows the timing of the 24P video signal, 83 shows the writing control timing of the frame memory 74, 84 shows the writing control timing of the frame memory 75, 85 shows the timing of the frame synchronizing signal of the 60I video signal, and 86 shows the timing of the 60I video signal.
First, the 24P video signal inputted to the input terminal 71 is written to the frame memories 74, 75, respectively. At this time, the writing/reading-out controller 76 performs writing by switching the writing target (frame memories 74, 75) by each frame of the 24P video signal according to the frame synchronizing signal of the 24P video signal inputted to the input terminal 72. The pull-down controller 78 performs a reading-out control of the frame memories 74, 75 through the writing/reading out controller 76 according to the frame synchronizing signal of the 60I video signal inputted to the input signal 73. Further, the pull-down controller 78 outputs the video signal being read out from the frame memories 74, 75 while making selection by the memory output selector 77. The video signal converted to the 60I video signal is outputted from the memory output selector 77 through the output terminal 79.
This will be described in more details in the followings. In the 24P input video signal 82 of FIG. 13, time-sequence four frames are denoted as A, B, C, D in order. Described is the case where the four frames are converted to the 60I video signals by synchronizing the time base.
First, the 24P input video signal 82 is written to the frame memories 74, 75 according to the frame synchronizing signal 81. That is, the writing control signal 83 for the frame memory 74 and the writing control signal 84 for the frame memory 75 are generated according to the frame synchronizing signal 81. Then, according to the writing control signal 83, the 24P video signal 82 is written to the frame memory 74 when the frame synchronizing signal 81 of the 24P video signal is HIGH. In the meantime, according to the writing control signal 84, the 24P video signal 82 is written to the frame memory 75 when the frame synchronizing signal 81 of the 24P video signal is LOW.
Next, the 60I video signal 86 is generated by reading out the video signals stored in the frame memories 74, 75 in order as described below. That is, in a first frame of the 60I video signal 86, after separating the frame A of the 24P input video signal 82 into a field Ao of an odd-number line and a field Ae of an even number line, the separated fields Ao, Ae are read out as the first frame of the 60I video signal 86.
In a second frame of the 60I video signal 86, after separating the frame B of the 24P input video signal 82 into a field Bo of an odd-number line and a field Be of an even number line, the separated fields Bo, Be are read out as the second frame of the 60I video signal 86.
In a third frame of the 60I video signal 86, while separating the frame B of the 24P input video signal 82 into the field Bo of an odd-number line and the field Be of an even number line, the frame C of the 24P input video signal 82 is separated into a field Co of an odd-number line and a field Ce of an even number-line field. Then, a frame is formed with the separated field Bo and the field Ce to be read out as the third frame of the 60I video signal 86.
In a fourth frame of the 60I video signal 86, after separating the frame C of the 24P input video signal 82 into the field Co of an odd-number line and the field Ce of an even number line, the separated fields Co, Ce are read out as the fourth frame of the 60I video signal 86.
In a fifth frame of the 60I video signal 86, after separating the frame D of the 24P input video signal 82 into a field Do of an odd-number line and a field De of an even number line, the separated fields Do, De are read out as the fifth frame of the 60I video signal 86.
In this manner as described above, for converting the 24P video signal to the 60I video signal, each field of the 24P video signal is read out by being separated into the fields, then the fields of each frame is read out in order under the state where a part of which is overlapped with each other in a repeated cycle, i.e. two fields (Ao:Ae)→three fields (Bo:Be:Bo)→three fields (Ce:Co:Ce)→two fields (Do:De)→ - - - .
In the device configuration shown in FIG. 12, the continuous four frames A-D of the 24P video signal are converted to the 60I video signal by arranging prescribed fields (Bo, Ce in the above-described case) with a part being overlapped with each other. The field arranging cycle of each frame at this time is 2 (no overlapping in the A frame): 3 (overlapping in Bo in the B frame): 3 (overlapping in Ce in the C frame): 2 (no overlapping in the D frame), so that this conversion system is called 2:3:3:2 pull-down system.
There are following problems in the conventional configuration. The 24P video signal is a video format widely used in movie films. The 60I video signal is an example of a standard video format for TV broadcasting. Thus, by converting the 24P video signal to the 60I video signal using the conversion format of the 2:3 pull-down system and the like, it enables to achieve the visual effect, similar to that of the movie film, in the standard displayed picture in TV broadcasting.
Recently, it has been desired to achieve the similar visual effect as that described above in a video system and the like used by amateur video creators. However, in order to achieve the above-described visual effect in the generally-used format of the 60I video signal and the like, the 24P video signal is required as an input video source. In order to obtain the 24P video signal, the filmed video data itself recorded in a film or an image pickup device capable of picking up the 24P video signal becomes necessary.
Moreover, for converting the 24P video signal to the 60I video signal, the format conversion of the 2:3:3:2 pull-down system or the like is performed. However, it requires two frame memories as the structural elements of such format conversion device. Also, writing/reading-out control for the frame memories, especially the reading-out control becomes complicated. Moreover, it requires the timing control (synchronizing the frames) when converting the 24P video signal to the 60I video signal. As described, the format conversion involves an increase in the circuit scale, increase in the cost, and complication of the control.